/*
 * Copyright (C) 2022 by Intel Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 * PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef AMX_POST_CONV_GEMM_RELU_ASS_HPP
#define AMX_POST_CONV_GEMM_RELU_ASS_HPP

#include "../amx_post_conv_gemm_relu_ass.h"

void amx_ref_gemm()
{
    tc conf = {
        1,                                                    // palette_id
        0,                                                    // startRow
        { 0,  0,  0,  0,  0,  0,  0,  0, 0, 0, 0, 0, 0, 0, }, // reserved - must be
                                                              // zero
        // tiles 0 to 3 for C_TMP, 4 for A and 5 and 6 for B
        { 64, 64, 64, 64, 64, 64, 64, 0, 0, 0, 0, 0, 0, 0, 0,
          0, }, // cols for 7 tiles used
        { 2,  2,  2,  2,  2,  16, 16, 0, 0, 0, 0, 0, 0, 0, 0,
          0 } // rows for 7 tiles used
    };

    amx_post_conv_gemm_relu_ass(&C_tmp_mem[0][0], &C_mem[0][0], &A_mem[0][0],
                                &B_mem[0][0][0], &conf, q_bias);
}

#endif
